1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device such as a static semiconductor memory device including multi-layered logic element units.
2. Description of the Background Art
FIG. 31 is a block diagram showing an example of a structure of a static random access memory (will be referred to as "static RAM" hereinafter).
In the figure, a memory cell array 50 includes a plurality of word lines and a plurality of bit line pairs which intersect with each other. Memory cells are disposed at respective intersection of the word lines and bit line pairs. The word lines of the memory cell array 50 are connected to an X-decoder 51, which receives an X-address signal through an X-address buffer 52. The bit line pairs of the memory cell array 50 are connected to a Y-decoder 54 through a transfer gate 53, which receives a Y-address signal through a Y-address buffer 55.
In response to the X-address signal, the X-address decoder 51 selects one of the word lines of the memory cell array 50. In response to the Y-address signal, the Y-address decoder 54 selects one of the bit line pairs of the memory cell array 50. The memory cell, which is disposed at the intersection of the selected word line and the selected bit line pair, is selected. Data is written into or read from the memory cell thus selected. The selection between the write and read of the data is carried out by a read/write control signal R/W applied to a read/write control circuit 56. In the data write operation, input Data Din is applied through a data input buffer 57 into the selected memory cell. In the data read operation, the data stored in the selected memory cell is externally sent therefrom through a sense amplifier 58 and a data output buffer 59 as data Dout.
FIG. 32 is a circuit diagram of a memory cell part in a static RAM having a memory capacity of 1M (mega) in the prior art disclosed in the Japanese Patent Publication No. 62-18997.
In the figure, a plurality of memory cells 101a-101n are connected between a pair of bit line pair 8a and 8b. Each of the memory cells 101a-101n is formed of two MOS field effect transistors (will be referred to as "MOSFETs") of an enhancement type for an inverter, as well as two high-load resistors 104 and 105, and two MOSFETs 6a and 6b for access.
Each drain D of the MOSFETs 4a and 4b is connected to one end of a corresponding high-load resistor 104 or 105, which is made of, e.g., polysilicon and has a high resistance. The other ends of the high-load resistors 104 and 105 are connected to power supply terminals 110 or 111, respectively. The sources S of the MOSFETs 4a and 4b are connected to a ground potential GND.
A gate G of the MOSFET 4a is connected to a node 14b. A gate of the MOSFET 4b is connected to a node 14a. Memory information is stored as potentials in a parasitic capacities 112 and 113 which are located between the node 14a and the ground potential GND and between the node 14b and the ground potential GND, respectively. The node 14a is connected to the bit line 8a through the MOSFET 6a for access, of which gate is connected to corresponding one of the word lines 7a-7n. The node 14b is connected to the bit line 8b through the MOSFET 6b for access, of which gate is connected to corresponding one of the word lines 7a-7n.
The bit lines 8a and 8b are connected to input/output lines I/O 119 and I/O 120 through MOSFETs 117 and 118, respectively, of which gates are connected to an input terminal 121 for receiving a column selection signal from the Y-decoder. The bit lines 8a and 8b are connected through MOSFETs 122 and 123 to connector terminals 124 and 125, to which a supply potential Vcc is applied, respectively. The connector terminals 124 and 125 are diode-connected and serves as loads to the bit lines. The MOSFETs 122 and 123 are provided for precharging the bit lines 8a and 8b. The power supply terminals 110 and 111 receive the power supply potential Vcc.
The memory cells described above operate as follows.
It is assumed that the data is read from the memory cell 101a when the node 14a of the memory cell 101a is at the "L" level, and the node 14b is at the "H" level. In this operation, the potential of the word line 7a changes from 0 V or a value near 0 V, which has been maintained in a non-selected state, to the supply potential Vcc or a value near Vcc, which is a value maintained in a selected state. Therefore, a current flows from the supply terminal 124 toward the ground terminal through the bit line load MOSFET 122, access MOSFET 6a, and inverter MOSFET 4a. Meanwhile, since the inverter MOSFET 4b is in the off-state, the current does not flow through a path extending from the supply terminal 125 to the ground terminal through the bit line load MOSFET 123, access MOSFET 6b and inverter MOSFET 4b. Therefore, the potential of the bit line 8a is set at a potential which depends on an on-state resistance ratio of the MOSFET 122 and MOSFETs 6a and 4a. The bit line 8b is set at a potential which is lower the supply potential Vcc by a threshold voltage of the bit line load MOSFET 123. In this manner, the sense amplifier 58 reads the stored information on the basis of the difference between potentials appearing on the bit lines 8a and 8b of each bit line pair.
In the SRAM of 1M (mega), however, the memory cell 101a includes the high load resistance 104a or 105, which is made of, e.g., polysilicon located between the terminal 110 or 111 and the node 14a or 14b. This cannot sufficiently achieve the high speed and stability of the read operation. It is assumed that the node 14b is held at the "H" level and the word line 7a is selected. In this state, the transistor 6b is turned on, and thus the current flows from the supply terminal 111 through the resistor 105 to the bit line 8b. However, the high-load resistor 105 reduces the voltage, and thus the intended increase of potential of the node 14b does not occur quickly. Therefore, the potential of the bit line 8b does not increase remarkably, so that the reading speed does not sufficiently increase. Further, there is not a significant difference between the potential of the node 14a holding the "L" level and the potential of the node 14b, which impairs the reliability of the reading operation.
In view of the foregoing background, SRAMs of 4M (mega) employ p-channel transistors instead of the high-load resistors 104 and 105 described above for improving the reliability and stability of the reading operation.
FIG. 33 is an equivalent circuit diagram of a memory cell in such SRAM.
In the figure, a memory cell forming one logic element unit is formed of six elements, i.e., driver transistors 4a and 4b, load transistors 5a and 5b, and access transistors 6a and 6b. The access transistors 6a and 6b are connected to the driver transistors 4a and 4b and the bit lines 8a and 8b, respectively, and have gates connected to the word line 7. The access transistors 6a and 6b serve to transfer data between the bit lines and the flip-flop. More specifically, an inverter formed of the driver transistor 4a and load transistor 5a is cross-coupled with an inverter formed of the driver transistor 4b and load transistor 5b to form the flip-flop for storing data. The SRAM of 4M is provided with a first layer, which includes the four transistors 4a, 4b, 6a and 6b formed on a substrate, and is also provided with a second layer, which is located above the first layer and includes two transistors 5a and 5b formed of polysilicon thin-film transistors (TFTs), for reducing a cell area. Thus, NMOS transistors, i.e., the driver transistors and access transistors are formed in the first layer 1, and PMOS transistors, i.e., the load transistors are formed in the second layer 2.
FIG. 34 is a perspective view showing a three-dimensional layout of transistors of memory cells in the conventional SRAM shown in FIG. 33.
In the first layer 1, there are formed the driver transistors 4a and 4b as well as the access transistors 6a and 6b. In the second layer 2, there are formed the load transistors 5a and 5b which are polysilicon TFTs. While there are four transistors in the first layer 1, i.e., on the substrate, only two transistors, i.e., polysilicon TFTs are formed in the second layer. Therefore, the second layer provided with the polysilicon TFTs has a superfluous area for two transistors according to calculation.
In practice, however, the transistor of bulk on the substrate (i.e., transistor having the source and drain formed in the semiconductor substrate) has the performance as the transistor which are different from that of the polysilicon transistors (TFT transistors). Therefore, these transistors have different gate lengths and gate widths in order to achieve sufficient functions as logic elements forming the memory cell. As a result, the area occupied by the four transistors of bulk balances with the that of the two polysilicon TFTs.
However, transistors of an SOI (silicon on insulator) structure, which are comparable to the transistors of bulk, can be formed in the second layer by utilizing a solid-phase growth method for increasing a grain diameter of polysilicon, or by utilizing a technique such as laser recrystallization for monocrystallization or a laminating technique. In the SRAM memory cell formed by the above technique or method, the bulk transistors in the first layer and the SOI transistors in the second transistors have nearly equal performance. Therefore, the area occupied by the access transistors of the NMOS type in the first layer can be equal to that of the load transistors of the PMOS type in the second layer.
FIG. 35 is a perspective view showing an element layout corresponding to the equivalent circuit shown in FIG. 33. FIG. 36 is a cross section of a structure in FIG. 35.
Referring to FIG. 35, the first layer is provided with the driver transistors 4a and 4b and access transistors 6a and 6b, and the second layer is provided with the load transistors 5a and 5b. As already stated, if the transistors in the second layer are formed comparably to the transistors of bulk, the respective transistors occupy the substantially equal areas. As shown in FIG. 35, therefore, the area occupied by the transistors in the first layer significantly differs from the area occupied by the transistors in the second layer 2. In the state shown in FIG. 36, two memory cells in FIG. 35 are disposed in parallel. As also can be seen from FIG. 36, superfluous spaces are formed in the second layer.
In conclusion, the development in the technique for forming the transistors in the second layer results in the layout of low efficiency relating to the degree of integration, so long as the memory cells employ the present structures.